Method and apparatus for operating the internet protocol over a high-speed serial bus

ABSTRACT

A method and apparatus of integrating the IEEE 1394 protocol with the IP protocol in which the IEEE 1394 high speed serial bus operates as the physical and link layer medium and the IP operates as the transport layer. There are differences in the protocols which require special consideration when integrating the two protocols. The IEEE 1394 configures packets with memory information and the IP operates under channel based I/O thereby necessitating a modification of the data transfer scheme to accomplish IP transfers over the IEEE 1394. Further, due to differences in packet headers, the IEEE 1394 packet header is modified to encapsulate IP packets. Moreover, in order to determine network packets quickly and efficiently, an identifier is inserted in each network packet header indicating that the packet should be processed by the network. Finally, in order to support the ability to insert or remove nodes on the network without a loss of data, the IP interface must not be disturbed. This is accomplished by maintaining constant IP addresses across bus resets which are caused by insertion or removal of nodes from the network.

BACKGROUND OF THE INVENTION

[0001] A. Field of the Invention

[0002] This invention relates to the operation of a high speed datanetwork which interconnects different application modules, and moreparticularly relates to a method and apparatus for operating IP protocolover a high-speed bus such as an IEEE 1394 high-speed bus.

[0003] B. Description of Related Art

[0004] When communication is necessary among heterogeneous systems (i.e.different vendors and standards), the software to communicate betweenthe systems can be extremely difficult to develop. The potential existsfor different vendors to use different data formats and data exchangeconventions so that the differing machines are unable to “talk” directlyto each other. To combat this potential problem, standardizingorganizations have established computer architectures and structures tofacilitate the communication between heterogeneous systems. One acceptedstructuring technique is layering. The communications functions arepartitioned into a vertical set of layers whereby each layer performs arelated subset of functions required to communicate with another system.Each layer then relies on the next lower layer to perform more primitivefunctions and to conceal the details of those functions as well as toprovide services to the next higher layer. In this manner, the largerproblem of communicating between differing systems can be structuredinto a discrete subset of layered subproblems.

[0005] One model of layering is the Open Systems Interconnection (OSI).The Open Systems Interconnection uses the layering framework with thegoal to create an open systems networking environment where any vendor'scomputer system, connected to any network, can freely share data withany other computer system on that network or linked network. Manycomputer systems have a structure based on the OSI model, whichorganizes the communication process into seven different categories andplaces these categories in a layered sequence based on their relation tothe user.

[0006] The three lowest layers in the OSI model (layers 1 through 3) arethe physical, link and network layers, each layer dealing with networkaccess. The physical layer is concerned with transmission ofunstructured bit stream over physical media, such as cables, and isconsidered to be the lowest layer. The link layer provides for thereliable transfer of information across the physical layer, sendingblocks of data with the necessary synchronization, error control, andflow control. The network layer determines how data is transferredbetween computers and addresses routing within and between individualnetworks.

[0007] One example of a physical and link layer medium is the IEEE 1394high speed serial bus. IEEE 1394 is a data transport bus that supportsup to 63 nodes per bus and up to 1023 buses. The bus can be a tree ordaisy-chained (devices connected in series) or a combination of both andcan support both asynchronous and isochronous data. Further, theInternet Protocol (IP) is a connectionless protocol (i.e. mode ofoperation in which a packet header is encoded with sufficientinformation to permit independent delivery of the packet) that operatesat the network layer. The IP protocol is a standard describing softwarethat monitors the internetwork addresses for different nodes, routesoutgoing messages, and recognizes incoming messages. IP, which works inconjunction with the Transmission Control Protocol (TCP), (andidentified as TCP/IP) provides communication across interconnectednetworks, between computers with diverse hardware architectures andvarious operating systems. TCP and IP are two of the more widely usedprotocols in the family of Internet protocols.

[0008] However, there are several problems when integrating the IEEE1394 protocols with the protocols. First, there are differences in theprotocols between the sender and the receiver of data. The IEEE 1394 isdesigned as a memory read/write bus where the sender of data must haveinformation on the receiver's memory structure. In particular, thesender or initiating node reads from or writes to the memory location ofthe receiver or target note. The sender node is required to know thememory architecture of the receiving node in order to perform memoryread/writes. In contrast, the IP protocol transfers data without thesender knowing about the receivers memory architecture. As such, thedata transfers of IP cannot be directly accomplished on the IEEE 1394architecture. Further, the IEEE 1394 is essentially a connectionlessacknowledged protocol. Each IEEE 1394 packet of data, other than apacket that is broadcast to all nodes, generates an acknowledgment fromthe receiver. If the acknowledgment indicates a failure in the receptionof the packet, the sender retransmits the packet. Second, the packetformats of the IEEE 1394 are incompatible with the IP packet formats. Apacket header is the portion of the message sent that containsinformation which guides the message to the correct destination.

[0009] Third, there are addressing problems when using the IP protocolas the transport protocol for data transfers over the IEEE 1394 bus. TheIP protocol uses logical addresses to identify each node in the networkwith the IP addresses as 32-bit values depicted in dotted-decimalfashion (e.g., 149.112.234.1 for IP host and 149.112.234.2 for anotherIP host). An application on one IP host that needs to transfer data toanother application on a different IP host will use the IP address todirect the data transfer (e.g., use the IP address 149.112.234.2 totransfer data to the second application). However, the IEEE 1394protocol requires the use of a physical address of the destination node.Thus, a conversion between the IP address to the IEEE address must beaccomplished before the data can be handed to the physical layer fortransmission.

[0010] Prior methods of obtaining the physical address, such as throughthe use of the Address Resolution Protocol (ARP), either cannot orshould not be used with the IEEE 1394 network. Ordinarily, when an IPhost wishes to obtain the address of a destination node, it broadcastsan ARP query with the IP address of the destination node. All IP hostson the local network receive the ARP broadcast and check to see if theIP address contained in the ARP query is the same as the local IPinterface address. The node whose address is equal to the addresscontained in the ARP query responds with an ARP response that containsthe physical address for that node. However, most ARP implementationscannot support the dynamic changing of the hardware address andtherefore cannot be used on an IEEE 1394 bus. The IEEE 1394 physicaladdress is generated dynamically by the IEEE 1394 and can change upon abus reset. The physical address of an IP interface is set at the time ofinterface initialization and cannot be changed without bringing the IPinterface down and then reinitialized with a new physical address. Ifthis is done, all of the IP traffic on the interface is stopped and isonly restarted after the IP interface is up again. Any TCP connectionsusing that interface will be torn down.

[0011] Further, the requirement of broadcasting an ARP inquiry and theaddress resolution latency are undesirable. All nodes on the network areforced to process the ARP request to determine if they have to respondto it. The determination of the physical address must be done quicklyenough so that no data is lost on the network. During thisdetermination, the data is buffered. However, the data can only bebuffered for a finite period of time due to physical constraints interms of memory requirements on the buffers and due to specificationconstraints in terms of the requirements of some protocols to process apacket of information within a certain period of time.

[0012] Another problem when integrating various heterogeneous systems isdetermining whether the data formats conform to a certain standard or acertain computer architecture. Components, such as computers and moduleson a network, receive many packets of information. In order to determineif the component should process the information, the component mustassess if the data format conforms with a certain standard or certaincomputer architecture. If the data format does not conform, thecomponent should not process the data. Otherwise, the data format shouldbe processed. Further, in order for a component to be able to processthe data more quickly, the component must quickly determine whether thepackets conforms. Otherwise, data might be lost.

[0013] Previous components have attempted to determine whether a packetshould be processed is by examining the format of the packet. Forexample, if the component is looking for a packet which is formattedunder the IP protocol, the component examines the packet to determine ifthe specific fields within the packet are within the bounds of a packetwhich is formatted under the IP protocol. If the packet is withinbounds, the component processes the packet. Otherwise, the packet isignored.

[0014] There are several problems with this scheme. First, thedetermination whether to process the packet is fairly intensive in termsof deciding whether specific fields in the packet conform to the IPprotocol. Second, a component can still be “fooled” into believing thata packet does conform to a certain protocol simply because the packetfalls within the bounds of that protocol.

SUMMARY OF THE INVENTION

[0015] In accordance with a first aspect of the invention, a method ofreconfiguring the bus line without disturbing the on-going traffic onthe bus is provided. The method includes the step of obtaining thenon-changeable address of the component, which does not change during abus reset, and the changeable address, which is assignable. The methodfurther includes the step of placing the non-changeable address andchangeable address in a look-up table. In addition, the network isreconfigured. The method further includes the step of determining thenon-changeable address of the component. The look-up table is examinedfor the changeable address which corresponds to the non-changeableaddress. In addition, the component is assigned the changeable addresswhich was placed in the look-up table prior to bus reset.

[0016] In accordance with a second aspect of the invention, a dataprocessing system is provided. The data processing system includes a busline and a module connected to the bus line. The module has a memorywhich contains a network identifier address. In addition, the dataprocessing system includes a network manager connected to the bus line.The network manager has a memory device and a processor with the memorydevice having a look-up table containing the network identifier addressand the changeable address. The processor has a comparator for comparingthe network identifier address in the look-up table with the networkidentifier address in the module.

[0017] In accordance with a third aspect of the invention, a method fordetermining whether to process an incoming data stream to a component isprovided. The method includes the step of determining the first packetidentifier contained in the first memory device of the first component.The method further includes the step the packet is formed having a fieldcontaining the first packet identifier. In addition, the packet is sentonto the bus. The method further includes the step of determining by thesecond component the second packet identifier contained in the secondmemory device of the second component. Further, the second componentreceives the packet from the bus and parses through the fields to obtainthe first packet identifier. The method further includes the step ofcomparing by the second component the parsed data with the second packetidentifier, and processing the packet if the parsed data equals thesecond packet identifier.

[0018] In accordance with a fourth aspect of the invention, a dataprocessing system is provided. The data processing system includes a busline and two modules connected to the bus line. The first module has afirst memory and a first processor, with the first memory containing afirst packet identifier. The first processor accesses the first memory,obtaining the first packet identifier, and forms a data streamcontaining the first packet identifier. The second module has a secondmemory and a second processor, with the second memory containing asecond packet identifier. The second processor has a comparator whichcompares the second packet identifier with the first packet identifierin the data stream.

[0019] In accordance with a fifth aspect of the invention, a method forsending a packet of data on a physical and link layer configured forpackets which include memory architecture information in the packet isprovided. The method includes the step of receiving the packet ofinformation at the link layer from the network layer from the sendermodule. The method also includes the step of placing header informationinto the packet which does not include memory architecture informationabout the receiver module and which conforms to sending the informationvia channel based I/O. In addition, the packet is transported to thereceiver module via the physical layer.

[0020] Accordingly, a primary object of the invention is to integratethe IP protocol with an IEEE 1394 high-speed bus.

[0021] Another object of the invention is to provide a means forinserting or removing nodes from a network at any level in the computerarchitecture without disturbing the on-going traffic on other nodes inthe network.

[0022] Still another object of the invention is to transfer IP packetson the IEEE 1394 using channel based input/output.

[0023] Still yet another object of the invention is to efficiently andcorrectly determine whether to process incoming packets of data.

[0024] These and other objects, features, and advantages of the presentinvention are discussed or apparent in the following detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A presently preferred embodiment of the present invention isdescribed herein with reference to the drawings wherein:

[0026]FIG. 1 is an exemplary application of the Remote Access andRouting Server;

[0027]FIG. 2 is block diagram of an example of a network and devicescomprising the Remote Access and Routing Server;

[0028]FIG. 3 is a block diagram of the Routing Device;

[0029]FIG. 4A is a block diagram of the Analog-Digital Call TerminatingDevice;

[0030]FIG. 4B is a block diagram of the Onboard T1/E1 NIC, Board ManagerSubsystem, DSP Subsystem and Shared Memory Subsystem of theAnalog-Digital Call Terminating Device;

[0031]FIG. 4C is a block diagram of the Application Co-Processor andShared Memory Controller of the Analog-Digital Call Terminating Device;

[0032]FIG. 4D is a block diagram of the Network Co-Processor Subsystemand Shared Memory Controller of the Analog-Digital Call TerminatingDevice;

[0033]FIG. 5 is a block diagram of the layered architecture of thenetwork;

[0034]FIG. 6A is a state machine of the initialization of the network;

[0035]FIG. 6B is a flow chart of the initialization of the networkcorresponding to the state machine in FIG. 6A;

[0036]FIG. 7A is the format of the IEEE 1394 address;

[0037]FIG. 7B is the format of the self-identification packet usedduring initialization of the network;

[0038]FIG. 7C is the format for the IP packet encapsulated in the IEEE1394 packet;

[0039]FIG. 7D is the format for the Get-Priority-Request;

[0040]FIG. 7E is the format for the Get-Priority-Response;

[0041]FIG. 8 is a block diagram of the network manager and module; and

[0042]FIG. 9 is the flow chart of the determination whether a packet issent from a compatible module.

DETAILED DESCRIPTION OF THE PREFERRED AND ALTERNATIVE EMBODIMENTS OF THEINVENTION

[0043]FIG. 1 refers to a Remote Access and Routing Server (RARS) 10 fora data processing system. The Remote Access and Routing Server 10integrates separate data communication entities via a public switchedtelephone network (PSTN) 22. The Remote Access and Routing Server 10provides remote access for mobile users and for individuals at homeoffices, access nodes for Internet service providers, and dial-up localarea network to local area network (LAN-to-LAN) routing capabilities forgeographically disperse corporate enterprises. For example, FIG. 1discloses one application of the Remote Access and Routing Server 10which allows communication between corporate offices (central and branchoffices) 12, 14, 16, homes and mobile users 18, 20. In a CorporateOffice or Internet Service Provider 12, the Remote Access and RoutingServer 10 is connected to a LAN 24 which is in turn connected to DataTerminating Equipment (DTE) 26, such as a computer, and to other devices28, 30. The Internet Service Provider 12 is also connected to theInternet. Branch Offices 14 or Small Offices 16 may also be connected tothe PSTN 22 via the Remote Access Routing Server 10. Further, Mobileusers 20 and Home Office users 18 may connect to the PSTN 22 via a modem32 or other data communication device.

[0044] The Remote Access and Routing Server 10 is comprised of astackable architecture whereby various suboperations of the RemoteAccess and Routing Server 10 are separated at the device level into aRouting Device 34, a Digital Call Terminating Device 36, andAnalog-Digital Call Terminating Device 38, allowing for expandability ofthe system based on a user's needs. The user may expand the system bysimply adding slices to the stack in modular increments. In this manner,the user's system may grow to match the user's needs. The Remote Accessand Routing Server 10 may also be combined into one system withoutseparation at the device level. Referring to FIG. 2, the modules areconnected via a network 40 with each device having its own power supply.The network allows inter-device communication in the systemarchitecture. The Routing Device 34, also known as a Router, the DigitalCall Terminating Device 36 and the Analog-Digital Call TerminatingDevice 38 are interconnected by the network 40, which is based upon theIEEE 1394 (Firewire). The Routing Device 34 is connected to a local areanetwork (LAN) 24 which is in turn connected to a management station 42.Each device is connected to the network 40 via a node which has anaddress. A single device may have multiple nodes connected to thenetwork 40. Further, each node attached to the network 40 has equalaccess to the data transfer services and share the available bandwidthwith other nodes. Each of the components have connectors to the network40 and can support a nominal 200 mb/s data rate. This applicationincorporates by reference U.S. Pat. No. 5,528,595 by inventors Walsh etal. entitled Modem Input/Output Signal Processing Techniques, whichdescribes further aspects of the Analog-Digital Call Terminating Deviceand the Routing Device.

[0045] The Routing Device 34 contains the router engine, the {fraction(10/100)} Mbit Ethernet® interface 56 and a network interface 54,referring to FIG. 3. The Routing Device 34 is the center of systemmanagement. It provides the functionality to route all of the protocolssupported by the Remote Access and Routing Server 10, is the simplenetwork management protocol (SNMP) agent for management of the system,and allows for synchronous serial interfaces for connection to a LAN ora Wide Area Network (WAN).

[0046] An Edge Server Device is a device which is placed at the edge ofthe Local Area Network. The Edge Server Device is similar to the RoutingModule in that it implements the network management components requiredas the primary network manager module on the network. The Remote Accessand Routing Server 10 may be implemented using a Routing Device 34, anEdge Server Device or a combination of both devices.

[0047] The Digital Call Terminating Device 36 contains two T1/E1 PrimaryRate Interface (PRI) connections, a network interface and the necessaryhardware to terminate two spans worth of Integrated Services DigitalNetwork (ISDN) originated calls. Depending on the country, either T1 orE1 is used. T1 is a standard for digital transmission in the UnitedStates, Canada, Hong Kong and Japan with a capacity of 1.544 M bits persecond. E1 is a standard for digital transmission in Europe with acapacity of 2.048 M bits per second. Call traffic, following processingby the Digital Call Terminating Device 36, is passed to the RoutingDevice 34, which in turn communicates with a LAN 24.

[0048] The Analog-Digital Call Terminating Device 38 is a single-spanT1/E1 access module designed to terminate calls of both analog anddigital origin. This call traffic, following processing by theAnalog-Digital Call Terminating Device 38, is passed to the RoutingDevice 34, which in turn communicates with a LAN 24. As shown in FIG. 2,a second Analog-Digital Call Terminating Device 39 can be integratedinto the network 40. Therefore, the Analog-Digital Call TerminatingDevices can be place in a star or daisy-chain topology with a secondAnalog-Digital Call Terminating Device acting as a repeater.

[0049] Referring to FIG. 3, a block diagram of the Routing Device 34 isshown. The central processing unit for the Routing Device 34 is aPowerPC™ 603 44 manufactured by IBM and Motorola and operating at 200MHz. Because the printed circuit board will use a BGA package for thePowerPC™, and will contain a 2.5 Volt regulator, the printed circuitboard can accommodate any PowerPC™ 603 or 604 device for adjustments ascentral processing unit capacity requirements change. The CPU chipset 48is the IBM 82660 family consisting of the 82663 buffer and 82664controller. This chipset 48 provides a glueless interface between thePowerPC™ 44, system memory (DRAM) 50, L2 cache 46, and the on-board PCIbus 52.

[0050] The L2 cache 46 consists of a single 16K×15 cache tag RAM with 432K×32 SSRAM devices to support the 512 KB of L2 cache. Furtherinformation on the IBM 82660 chipset 48 is in IBM27-82660 PowerPC™ toPCI Bridge and Memory Controller User's Manual, IBM, SC09-3026-00, 1996.

[0051] Main memory is 64 bits in width and consists of 16 MB of basememory plus field upgrade capacity to 144 MB. Base memory consists ofeight 1 M×16 60 ns EDO DRAM devices soldered to the PCB for reliabilityand low cost. The PCB contains one 168-pin DIMM socket for memoryexpansion to 24, 32, 48, 80, or 144 MB total capacity using a 8, 16, 32,64, or 128 MB DIMM respectively. Expansion memory is EDO for higherperformance. Boot memory contains the CPU's primary bootstrap code to beexecuted upon hardware reset and consists of a software-locked segmentof main storage flash. This allows primary bootstrap code to befield-updated in the unlikely event that becomes necessary. Storagememory (Bulk Flash 64) is erasable and supports the operational code andthe application's file system. It consists of 4 MB of flash memory, withprovision for larger factory-installed sizes. The printed circuit boardsupports four flash devices so that the board is populated with two 2MB×8 devices for a total of 4 MB. The maximum configuration is 8 MB with2 MB×8 devices. Memory is accessible as 32 64 KB blocks per device withboot memory and storage memory share the same physical device.

[0052] Storage memory consists of two Intel 28F016SC devices or two AMD29F016 devices, with separate programming algorithms for the Intel orAMD devices. A command user interface serves as an interface between theCPU and the internal operation of the device. A valid command sequencewritten to the device initiates automatic execution of algorithms andtimings for block erase, byte write, and lock-bit configurationoperations. A block erase operation erases one of the 64 KB blockstypically within one second wherein each block may be erased 100,000times.

[0053] The Non-Volatile Memory is an EEPROM 66 consisting of 512 bytes.The EEPROM 66 is written with the serial number and configuration dataas part of the manufacturing process. Non-volatile memory consist of oneNM93LC66 device with locations individually addressable (as 16-bit“registers”). The non-volatile device is accessed serially via athree-wire interface (select, clock, data); however, this serial accessis under control of the PCISC2 FPGA, which makes the EEPROM 66 visibleto software through a conventional register set.

[0054] Two UARTs (Universal Asynchronous Receiver Transmitter) 70 aresupported in the Routing Device, as shown in FIG. 3. The first is aConsole Port UART and is customer-accessible via a front-panel DB9connector. The UART complies with the ANSI RS-232-E and ITU V.28standards, is configured as a DTE interface, supports hardware RTS-CTSflow control, contains 16-byte transmit and receive FIFOs, and supportsthe required asynchronous communication rates of 9600, 19200, 38400,57600, and 115200 Baud. The Console Port UART consists of one 16C550CFNdevice clocked at 3.6864 MHz and one Maxim MAX241 transceiver.

[0055] The second UART is a Debug UART. The debug port is terminatedinternal to the Routing Device via a header, is compliant with ANSIRS-232-E and ITU V.28 standards, is configured as a DTE interface,supports hardware RTS-CTS flow control, contains 16-byte transmit andreceive FIFO's, and supports the required asynchronous communicationrates of 9600, 19200, 38400, 57600, and 115200 Baud. The debug portconsists of one 16C550CFN device clocked at 3.6865 MHz, and one MaximMAX241 transceiver. The Real-Time Clock 68 is used to provide date(year, month, day of month, day of week) and time (hours, minutes,seconds, hundredths). In addition to time/date availability, the devicefeatures alarm time comparison, programmable clock tick interruptgeneration, a small number of bits of general purpose non-volatile RAM,and automatic storage of the date/time of last power failure. TheReal-Time Clock 68 consists of a DP8573A device with a dedicated 32.768kHz crystal and capacitor backup power.

[0056] The Watchdog Timer 72 detects unusual operation by interruptingand then resetting the module if the timer 72 has been enabled but notbeen tickled in nominally 1.6 seconds. Upon reset, the watchdog timer isdisabled, and requires an explicit software operation to enable it. Onceenabled, software cannot disable it without allowing it to expire.Expiration of the watchdog causes a non-maskable interrupt (NMI) tooccur. The Watchdog Timer 72 consist of one Maxim MAX697 supervisordevice with assistance from the PCISC2 FPGA.

[0057] Voltage tolerance monitoring is provided on two critical voltages(+5.0 Volts, +3.3 Volts). Monitoring of +5.0 Volts is provided by thepower supply unit. Monitoring of the Power supply unit generated +5.0and +3.3 Volts is performed by on-board Routing Device circuitry, asdiscussed subsequently. If any voltage becomes out-of-tolerance, theboard will be placed in a reset condition and held until theout-of-tolerance condition passes. The +5.0 and +3.3 voltages aremonitored on-board so as to generate a proper power-up reset signal tothe board. The +2.5 Volt signal, generated on-board, is not monitored,because it is derived from a high-MTBF regulator, and because a resetsignal is more accurately derived by monitoring that regulator's inputvoltage (+5.0/+3.3). On-board voltage monitoring will be performed bythe voltage detection subsystem of the Maxim MAX 697 supervisor device.

[0058] The Routing Device 34 is equipped with a reset button 76 whichcauses an immediate hardware reset of the entire module. This isrequired for debugging and catastrophic error recovery under otherwiseunanticipated conditions. The button 76 drives the Maxim MAX 697supervisor device, which is responsible for reset generation and timing.

[0059] A digital thermometer-thermostat device is used to sense on-boardtemperature. The device's alarm setpoint is programmed at time of boardmanufacture so that an alarm is generated and routed to a statusregister when this setpoint is exceeded. This setpoint is the “hard”setpoint beyond which proper operation cannot be guaranteed. Thetemperature sensor device is accessed serially via a three-wireinterface (select, clock, data); however, this serial access is undercontrol of the PCISC2 FPGA 58, which makes the device visible tosoftware through a conventional register set. In addition to this meansof measuring on-board temperature, the power supply unit will be capableof detecting an over-temperature condition within the power supply unititself The basic user interface consists of an LCD (liquid crystaldisplay) panel 74, six buttons 76, and two LEDs (unit power and unitstatus) 74. The LCD 74 and buttons 76 reside on a subassembly whichattaches to the main PCB via a cable and connector. The LCD 74 andbutton peripherals 76 are connected to the PCISC2 FPGA 58.

[0060] The PCI Bus 52 is provided by the IBM82660 chipset 48. Itoperates at 3.3 Volts and is compliant with PCI Specification Revision2.0. The PCI Bus 52, like the rest of the Routing Device 34, is operatedin big endian (also known as non-Intel) byte-order mode. Big endian is aformat for storage or transmission of binary data in which the mostsignificant byte comes first. The reverse convention is called littleendian. PCI device configuration registers are required to operate inlittle endian mode for PCI compliance; therefore, software reordersbytes only when reading PCI device configuration registers. Twosingle-width PMC Connector slots 60 are provided for future expansion.

[0061] PCI based systems require a set of bus support functions(referred to as Central Resource Functions) that are usually notprovided by a PCI Bridge such as the IBM82660 48. The Central ResourceFunctions in this design include a central arbiter, interruptcontroller, and miscellaneous logic for individual device selectionduring PCI configuration cycles. These functions are provided in thePCISC2 FPGA device 58. In addition to the Central Resource Functions,this device 58 provides a bridge to a slower-speed eight-bit bus (X-bus)62 which supports all non-PCI peripherals (flash memory 64, UARTs 70etc.). The PCISC2 FPGA 58 provides bus buffering and control, addressdecoding, and chip select generation for X-Bus peripherals. TheEthernet® Interface 56 connects to the Ethernet® LAN subsystem. TheNetwork Interface 54 connects to the IEEE 1394 . The Network Interface54 contains the =5 physical layer interfaces (PHYs), link layercontroller (LLC), and the power subsystem. The Network Interface 54 alsoprogrammed to communicate with the PowerPC™ 44 whereby the NetworkInterface 54 indicates to the PowerPC™ 44 when a packet has beenreceived or sent. Software code, which is resident in System Memory 50,is executed by the PowerPC™ 44 to control the operation of the NetworkInterface 54. The software code is discussed subsequently in FIGS. 5-9.

[0062] The Edge Server Device is designed based on industry standardpersonal computer architecture using commercially available components.Intel®V Pentium Pro® processor-based mother boards are used. Further theoperating system is Windows NT 4.0. Therefore the Edge Server deviceuses the native remote access service for Windows NT™ to provide thefunctionality of a dialup router. The Edgeserver Module originates andterminates calls from the Analog-Digital Call Terminating Device 38 andthe Digital Call Terminating Device 36. Therefore, the Edgeserver Moduleis able to answer and authenticate inbound calls and route them onto acorporate LAN using the IP protocol. The power subsystem, as shown inblock 54 of FIG. 3 is integrated into the Edge Server device in order topower the PHYs and also power the network power bus. Further, the EdgeServer device includes a Network Interface which programmed tocommunicate with the microprocessor whereby the Network Interface 54indicates to the microprocessor when a packet has been received or sent.Software code, which is resident in System Memory 50, is executed by thePowerPC™ 44 to control the operation of the Network Interface 54. Thesoftware code is discussed subsequently in FIGS. 5-9.

[0063] Referring to FIG. 4A, a block diagram of the Analog-Digital CallTerminating Device 38 is shown. The Onboard T1/E1 NIC (Network InterfaceCard) 78 provides an interface between the T1/E1 telephone lines and theremainder of the Analog-Digital Call Terminating Device 38. The BoardManager Subsystem 80 executes the software which controls the calls toand from the T1/E1 line. The Board Manager Subsystem 80, when receivingdata from the T1/E1 line, sends the data to the DSP Subsystem 82 whichcontains 24 modems. The DSP Subsystem 82 may be expanded to include 30modems. Subsequently, the Board Manager Subsystem 80 sends the data tothe 4-Port Shared Memory Subsystem 84. The Network Co-ProcessorSubsystem 88 then takes the data in the Shared Memory Subsystem 84 andsends it onto the Network 40 for routing by the Routing Device 34. Whensending data onto the T1/E1 line, the process is reversed in that thedata is taken from the Shared Memory Subsystem 84, sent to the DSPSubsystem 82, through the Onboard T1/E1 NIC 78, and then to the T1/E1line.

[0064] The various subcomponents of the Analog-Digital Call TerminatingDevice 38 communicate with each other via data buses, as shown in FIG.4A. Further, there is a local time division multiplex line connectingthe DSP Subsystem 82 with the Onboard T1/E1 NIC 78, as discussed infurther detail subsequently.

[0065]FIG. 4B shows a more detailed block diagram of the Onboard T1/E1NIC 78, Board Manager Subsystem 80, Shared Memory Subsystem 84 and DSPSubsystem 82 of the Analog-Digital Call Terminating Device 38. Thepassive circuitry 90 contains transformers and protection devices toprotect from any spikes in the voltage on the T1/E1 line. The passivecircuitry 90 also matches the impedance to the T1/E1 line. The LineInterface Unit (LIU) 92, part number LXT361, is the physical layerinterface, acting as a line driver/receiver. The Framer 94 handles allof the T1/E1 framing and transmit framing tasks. The Time-SlotInterchanger (TSI) 96 allows the time slots to be remapped when sentback onto the T1/E1 line. The 64 channel Local Time Division Multiplex(TDM) bus is connected between the Time-Slot Interchanger 96 and the DSP108. The Board Manager PowerPC™ model number 403GCX-66 also communicateswith memory devices, FLASH 104 and DRAM 106. The Board Manager Addressand Data Bus 107 connects the Board Manager 124 with the DSP Subsystem82, the Shared Memory System 84 and the Onboard T1/E1 (NIC) 78, asindicated by the data paths in FIG. 4A (81, 83, 79).

[0066]FIG. 4C shows a more detailed block diagram of the ApplicationCo-Processor 126, PowerPC™ model number 403GCX-66, in combination withthe Shared Memory Controller 128 and SRAM 130 and DRAM 132 memorydevices. The Application Co-Processor Address and Data Bus 131 connectsthe Application Co-Processor 126 with the Shared Memory Controller 128,the SRAM 130 and DRAM 132, as indicated by the data path in FIG. 4A(85).

[0067]FIG. 4D shows a block diagram of the Network Co-Processor 134,PowerPC™ model number 403GCX-66. The Network Co-Processor 134 is theinterface for the Analog-Digital Call Terminating Device 38 to the IEEE1394 . The System Controller FPGA 138 is for monitoring the primarypower supply and the backup power supply, allowing the NetworkCo-Processor 134 to control the local power supply. The NetworkInterface 150, similar to the Network Interface 54 for the RoutingDevice 34, connects to the IEEE 1394 . The Network Interface 150contains the physical layer interfaces (PHYs), link layer controller(LLC), and the power subsystem. The Network Interface 150 is alsoprogrammed to communicate with the Network Co-Processor 134 whereby theNetwork Interface 150 indicates to the Network Co-Processor 134 when apacket has been received-or sent. Software code, which is resident inDRAM (Dynamic Random Access Memory) 136, is executed by the NetworkCo-Processor 134 to control the operation of the Network Interface 150.The software code is discussed subsequently in FIGS. 5-9. The NetworkCo-Processor Address and Data Bus 135 connects the Network Co-Processor134 with the Shared Memory Controller 128, as indicated by the data pathin FIG. 4A (87).

[0068] Referring to FIG. 5, a system using a layered architecture modelis shown with the IEEE 1394 high speed serial bus 40 providing thephysical and link layer functions and the TCP/IP 152, 154 serving as thetransport layer. The Bus Management Protocol (BMP) 156 is responsiblefor management of the network, such as the selection of the networkmanager and the optimization of the IEEE 1394 bus. The User DatagramProtocol (UDP) 158 is also a transport layer protocol providingconnectionless mode protocol.

[0069] The network uses the IP protocol as the transport protocol fordata transfers over the IEEE 1394 bus 40. The IP protocol uses logicaladdresses to identify each node in the network with the IP addresses as32-bit values depicted in dotted-decimal fashion (e.g., 149.112.234.1for one application and 149.112.234.2 for another application). Anapplication that needs to transfer data to another application will usethe IP address to direct the data transfer (e.g., use the IP address149.112.234.2 to transfer data to the second application). Each node onthe network is configured with an IP address within the network rangethat uniquely identifies the node. For a network supporting up to 63nodes, it is sufficient to use a single Class C IP network address. Thenetwork can support IP address assignment to the individual modules inthe network. Further, for a single IP network, the IP addresses areassigned such that all nodes are on the same IP network and no two nodeshave the same IP address. The IP addresses are assigned to the nodesthrough the Net-Topology-Update packet, which is described subsequently.

[0070] On the other hand, IEEE 1394 uses the physical address of thedestination node. FIG. 3A is the format of the IEEE 1394 physical layeraddress. It uses a 16-bit wide address formed by the concatenation ofthe 10-bit bus number and the 6-bit node number. The network may supportthe bridging of multiple IEEE 1394 buses with the differing busesdistinguished by the 10-bit bus number. In an embodiment which uses asingle IEEE 1394 bus configuration, the first 10-bits of the IEEE 1394address need not change across bus resets. The 6-bit node number resultsin a total address space of 64 addresses per IEEE 1394 bus. AddressFFFF₁₆ is used as the broadcast address for the bus, thereby resultingin an effective address space of 63 addresses. The 6-bit node addressfor the IEEE 1394 is generated dynamically by the 1394 bus during businitialization, resulting in a potentially different IEEE 1394 addressfor the same node across bus resets. A bus reset occurs whenever thereis a reconfiguration of the network (i.e. whenever a node is inserted orremoved from the network). Therefore, the IEEE 1394 is unlike otherphysical layers in that it is not programmed with an address for thenode which is constant when the system is reconfigured.

[0071] In order to transfer data over the IEEE 1394 physical layer, aconversion between the IP address to the physical address must beperformed. However, this conversion cannot be accomplished through priormethods such as an Address Resolution Protocol (ARP) since most ARP'sare not designed to support dynamic changing of the hardware address(which the IEEE 1394 does) and since the ARP is inefficient sending abroadcast request. This conversion may be accomplished through anaddress resolution scheme whereby a look-up table is used to map the IPaddress to the appropriate IEEE 1394 address. Though implemented usingIP and IEEE 1394 addresses, other protocols may be substituted for theIP or IEEE 1394 protocols when implementing the address resolutionscheme using a look-up table. Further, the address resolution scheme maybe implemented at any layer of the computer architecture (e.g.,physical, data link, network, transport, session, presentation, orapplication layers).

[0072]FIG. 6A is a state machine and FIG. 6B is a flow chart of theinitialization process of the network with the preferred softwarelisting below. The software, which is attached as an Appendix andincorporated herein by reference, is written in the “C” programminglanguage and is executed on the IBM/Motorola PowerPC™ microprocessor.The software implements the procedures disclosed in FIGS. 5, 6A, 6B, 8,and 9. The reader's attention is directed to the notice regardingcopyright set forth at the beginning of this document.

[0073] Referring to FIG. 6A, the Bus Reset state 162 is entered when asystem power up occurs or when a node is inserted in or removed from thenetwork. The main function of this state is to ensure that the resetsignal is propagated to all the nodes so that all IEEE 1394 nodes enterthe reset phase. The Bus Reset state 162 may be entered at any phase ofnetwork operation in order to maintain maximum flexibility of thesystem, as denoted by the arrows in FIG. 6A. In the Bus Reset state 162,the IEEE 1394 physical layer chip detects the insertion or removal of anode and sends a reset signal onto all of the ports for a period of timeto ensure that the entire bus sees the signal. In other words, a busreset occurs whenever the network is reconfigured by insertion orremoval of a node. The 1394 link controller also sends an interrupt toindicate the entry into Bus Reset 172, as shown in FIG. 6B. The previousaddress resolution table (based on the Net-Topology-Update discussedsubsequently) and any output packets buffered in the 1394 driver areflushed. All IP traffic on the IEEE 1394 interface is stopped andresumed only upon entering the Data Transfer phase. In keeping with theability to insert or remove a node from the network without affectingdata traffic between other nodes in the network, existing TCPconnections between nodes, other than the node being inserted/removed,are not reset upon entering the Bus Reset state. Further, the TCP/IPprotocol is not informed of any change in the state of the network andthe applications using the network are not notified of the bus resetevent. The TCP/IP protocol itself is not affected in any way and datatransfers from the application to the protocol stack continue as before.All output data on a TCP session will be buffered by the protocol stackduring the initialization phase until the flow control window closes174. At this point, the application will not be able to transfer moredata to the protocol stack. When the Data Transfer phase is entered, theflow control window will be opened again, allowing for data transfers tocontinue on the session. For data which is input, upon entering the BusReset phase, input data buffered by the TCP session will continue to betransferred to the application. Once all buffered input data has beentransferred to the application, no more data will be transferred to theapplication until the Data Transfer phase is entered.

[0074] Next, the tree identify state 164 results in the ordering of theIEEE 1394 bus into a logical tree with one node as the root 176. Eachnode waits to receive a signal from a “child” node, which is of lowerpriority. If the node receives a “child” signal, then it sends a messageto its “parent” indicating that the node is a “child” and that the nodehas a “child” as well. In this manner, the logical tree is formed sothat all the nodes know their place in the tree, from the lowest leaf tothe highest root. The root node, which has the highest natural priorityfor access to the IEEE 1394 bus, is selected via an arbitration processin the case of multiple root-capable nodes.

[0075] Each node forgets its IEEE 1394 address it had prior to the busreset. The lowest leaf then gets the node address of zero. The nexthighest node receives the node address of one, and so on until the rootnode receives the highest IEEE 1394 node address. If a module is removedor inserted, the tree structure may be disrupted so that the IEEE 1394addresses, which are based on the tree structure, may be differentacross bus resets. Therefore, the IEEE 1394 addresses change dynamicallysince software is not able to guarantee that a node will have a certainIEEE 1394 address across a bus reset.

[0076] After the logical tree is formed, the self-identify phase 166 isentered. Each node on the network acquires a new 1394 physical addressand advertises it to the network by broadcasting the self-identificationpacket 176. The format of the self-identification packet is referred toin FIG. 7B. The first two bits (10) indicate that the format is aself-identification packet identifier. The phy_ID is the physical nodeidentifier of the sender of the packet. Other items in theself-identification packet include: L (active Link transaction layer);gap_cnt (current value of node's gap count); sp (speed capabilities);del (worst case repeater delay); c (node is contender for manager of thenetwork, which is discussed subsequently); pwr (power consumption); p0,p1, p2 (port status); i (indicates if node initiated reset); and m(indicates if a second self-identification packet will be sent).

[0077] The self-identification packets are essentially broadcast on thenetwork with each node building a table of self-identification packetsto determine the 1394 address of the root node 34. The root node has thehighest 1394 address so that, upon completion of the self identify phase166, all nodes on the network know the 1394 address of the root node176.

[0078] After the self-identify phase 166, the root node selects the nodewhich will be the manager of the network based on theself-identification packets during the Manager identify phase 168. Theroot node searches the list of self-identification packets to determinethe manager capable nodes in the system. If there are no manager capablenodes, the root node detects an error condition. If the root nodedetermines that there is at least one manager capable node, the rootnode broadcasts a Get-Priority-Request message 178 to obtain thecapability, priority, current IEEE 1394 address and the networkidentifier (NID) of each node.

[0079] Referring to FIG. 7D, the Get-Priority-Request is sent to obtainthe network identifier and the priority of all the nodes on the network.The Get-Priority-Request consists of: total_length (16 bits) which isthe total length of the message in octets; message_code (16 bits) whichis set to one (1) for Get-Priority-Request; source ID (16 bits) which isthe IEEE 1394 node ID of the sending node and is the concatenation ofthe 10-bit source bus ID and 6-bit physical address (as shown in FIG.7A); and reserved (16 bits) which is set to zero(0).

[0080] The network identifier is a unique 32-bit network identifierwhich is hardwired into each node during manufacture in the factory. Thenodes then send Get-Priority-Responses 178. Based on theGet-Priority-Response of each node to the Get-Priority-Request message,the root node selects the manager of the network. Further, theGet-Priority-Response is used to maintain consistency of IP addressesacross bus resets, as discussed subsequently.

[0081] If the root node itself is selected as the manager of thenetwork, the initialization continues 180. However, if a node other thanthe root node is selected as the manager of the network, the root nodethen broadcasts a message to enable root connection to the node whichwas selected as the manager of the network upon the next bus reset 182.The root node also transmits the look-up table of addresses, which isdiscussed subsequently, to the node which was selected as the manager ofthe network 182. The current root node then initiates a second bus resetso that the new configuration will take effect. Upon the second busreset, the node which was already selected as the manager of thenetwork, upon reset, will also be chosen as the root node so that theinitialization continues.

[0082] The manager of the network 190 then assigns the IP addresses tothe nodes 184. In order to support the hot-swap capability, theassignment of IP addresses must be done such that nodes that wereassigned IP addresses before this bus reset (i.e. the bus reset thatcaused the manager of the network to be selected) must be assigned thesame IP address. Otherwise, whenever a node is inserted or removed fromthe network, the IP interface must be brought down with all of the IPdata structures being reinitialized. Because of this hot-swapcapability, the IP interface is left in tact with the IP still“believing” that it is talking to the physical and link layers as beforethe insertion or removal of the node from the network.

[0083] In order to accomplish this hot-swap feature, the manager of thenetwork 190 uses a look-up table 198 in a memory device 196, such as aRandom Access Memory (RAM) device. The look-up table 198 contains thenetwork identifier (NID) and the corresponding IP address and IEEE 1394address prior to the bus reset. Besides being unique for each node, thenetwork identifier never changes for the lifetime of the node. Thus,while the IEEE 1394 node address as well as the IP node address maychange upon bus reset, the network identifier does not. Therefore, thenetwork identifier acts as a permanent unique node identifier, and the32-bit network identifier space is sufficiently large enough such thatit may be segmented-to allow for various pieces of information specificto the node, such as module type information. The 32-bit networkidentifier does not have any specific formatting requirements other thanthe requirement that it be unique. Further, the NED 212 is programmedinto the node using a ROM 210, as shown in FIG. 8, or other means whichwill allow for the network identifier address to be constant across abus reset. The network identifier, while programmed at the factory, mayalso be programmed by the user. In addition, the network identifier maybe changeable during periods of operation but other than during aninsertion or removal of a node from the network; however, as statedpreviously, the network identifier must be constant across an insertionor removal of a node from the network. Other means may be employed whichallows for the node to maintain a unique node identifier between busresets. For example, the network identifier can be stored in flashmemory or some other memory which will be constant across a bus reset.Or, the network identifier can be taken from other sources in themodule, such as the serial number which is programmed into the module atthe time of manufacture.

[0084] Based on a look-up table 198, referred to in FIG. 8, and based onthe Get-Priority-Responses (which contains the network identifier forthe specific node), the manager of the network determines the previousIP address for a specific network identifier. The Get-Priority-Responseis sent in response by a node to a Get-Priority-Request message. Thismessage is sent to the address specified in the Get-Priority-Requestmessage in the “source_ID” field, as shown in FIG. 7D. Referring to FIG.7E, the Get-Priority-Response consists of: total_length (16 bits) whichis the total length of the message in octets; message code (16 bits)which is set to two (2) for Get-Priority-Response; source_ID (16 bits)which specifies the IEEE 1394 node ID of the sending node and is aconcatenation of the 10-bit source bus ID and the 6-bit IEEE 1394physical address (as shown in FIG. 7A); priority_level (8 bits) which isthe priority level of this node in the range of 0-255 with 255 being thehighest priority; capability_flags (8 bits) which is the bit flagsindicating the management capabilities of this contender; andsource_PNID (32 bits) which is the network identifier for the node (asdiscussed previously).

[0085] The manager builds a temporary look-up table which maps thecurrent IP addresses for the specific network identifiers. The managerthen uses its comparator 194 in it processor 192 to compare the valuesin the historical look-up table 194 which contains the networkidentifier and the previous IP and IEEE addresses with theGet-Priority-Responses. The processor 192 then determines the previousIP address for the specific network identifier. The network manager 190then assigns the previous IP address before the bus reset to the nodefor the specific network identifier. After all of the nodes are assignedtheir previous IP addresses, a new look-up table is created, deletingthe nodes which were removed and adding the IP and IEEE 1394 addressesfor the nodes that were inserted. Thus, based on the look-up table, eachnode which was in operation prior to bus reset will be assigned the sameIP address as before the bus reset.

[0086] After the IP and IEEE 1394 addresses are determined, the gapcount, which is a number that is used by the IEEE 1394 physical layerchip in the calculation of the time between packet gaps, is optimized186. The gap count is a factor of the number of nodes connected to thebus, and is set to the maximum value of 3F₁₆ upon bus reset. The manageroptimizes the gap count by calculating a new gap count for the IEEE 1394bus topology, and then broadcasts the new gap count to all of the nodesconnected to the bus.

[0087] The final phase of the state diagram in FIG. 6B is the DataTransfer State 170 and is entered after completion of the ManagerIdentify state 168. The Manager Identify state 168 is completed when theresults of the IP address assignment and the IEEE 1394 addresses arebroadcast to all nodes 188, which is the Net-Topology-Update. Uponreceipt of the results of the address assignment, a node resumestransfer of IP packets on the IEEE 1394 interface. Further, all nodesremain in the Data Transfer phase until a bus reset is caused on thenetwork.

[0088] In an alternative embodiment, the address resolution scheme canprevent disturbances in the on-going traffic in both higher and lowerlayers in the computer architecture. In the previous embodiment, theon-going traffic was not disturbed at the IP layer and above. Further,due to limitations in the IEEE 1394 specification, which only allows fordynamic addressing, the addresses for the IEEE 1394 cannot be maintainedwith certainty across bus resets. However, for protocols which allow forassignment of addresses at the physical and link layers, rather thandynamic generation or programmed addresses during manufacture, theon-going traffic at the link layer and below can be maintained due tocontinuity of addresses across bus resets. During a bus reset at thephysical layer, the data on the physical layer bus may be corrupted dueto the insertion/removal of a new node (which caused the bus reset).However, data on the drivers, which were previously formatted but notyet put out on the bus, can be maintained through the address resolutionscheme. Therefore, using both the network identifiers and the look-uptable which contains the previous addresses for the nodes, the sameaddresses can be assigned so that traffic can remain undisturbed acrossa bus reset. Further, the address resolution scheme can also be used inswapping any connection at any layer or hierarchy of the computerarchitecture, from the physical layer to the application layer.Moreover, the process and apparatus can be used with any computerarchitecture to protect disturbances at any node within the computerarchitecture.

[0089] In this manner, different modules may be inserted or removed fromthe network without disturbing the on-going traffic on the system. Forexample, referring to FIG. 2, nodes such as the Router device 34,Digital Call Terminating Device 36, and Analog-Digital Call TerminatingDevice 38 can be inserted or removed from the network without disturbingthe on-going traffic. Ordinarily, the Router Device 34 is chosen as themanager of the network, so that the Router Device 34 will contain thelook-up table which is used to assign the same IP addresses for otherdevices such as the Digital Call Terminating Device 36 or theAnalog-Digital Call Terminating Device 38 as before the insertion orremoval of another module on the network 40.

[0090] A second aspect which is incompatible between the IEEE 1394 andthe IP are the protocols between the sender and receiver. The IEEE 1394assumes that the sender or receiver is not an “intelligent” device andis not intended for channel based I/O. In other words, the IEEE 1394link layer specification includes a memory read/write data transferscheme, where the requesting node specifies the memory location of theread/write action in the destination node. Therefore, the IEEE 1394protocol includes information on the sender's or receiver's memoryarchitecture, such as the specific location in memory for the read orwrite. IP, on the other hand, is intended for channel based I/O andassumes that the sender or receiver is sufficiently intelligent toprocess the data without memory architecture being included in thepacket. To reconcile this difference, the data transfer scheme asspecified by the IEEE 1394 is modified to transfer IP packets over IEEE1394 . The network transfers the packets using addressed data writes totransfer data. Addressed data transfers allow for more flexibility inthe handling of the data by the receiving node, whose memoryarchitecture can be very different from the sending node. Further, thesending node need not be aware of the memory architecture of thereceiver which allows for greater scaleability of the system.

[0091] As referred to in FIG. 7C, the Common Packet Header (CPH)contains the information that the IEEE 1394 examines to determine therouting of the packet. The IEEE 1394 does not have a field in which todetermine what type of protocol is encapsulated in its packet, i.e. whattype of payload it is carrying. Further, the common packet header of theIEEE 1394 ordinarily contains the destination offset field in order tocomply with the IEEE 1394's requirement of including memory architectureinformation.

[0092] Modification of the IEEE 1394 packet header is done to integratethe IEEE 1394 with the IP protocol. In particular, the IEEE 1394,through its specification, has a field in the header which has memoryinformation (i.e. where the packet is to be written to or read from) ofthe target of the packet of data. However, to integrate the twoprotocols, the field is modified, putting in the “protocol_type” fieldin the packet header. This is done so that the module that receives thepacket will examine the field with the protocol type and determine fromwhere the packet was sent from (i.e. the IP or the BMP). In this manner,the receiver module determines what type of data it is carrying via the“protocol_type” field in the packet header as shown in FIG. 7C. Theprotocol_type field is 16 bits and specifies the protocol of the packetencapsulated in the data field. For the architecture disclosed in FIG.5, the protocol_type field values are either BMP (Bus ManagementProtocol) or IP (Internet Protocol) to signify to the IEEE 1394 that thedata field encapsulated in the IEEE 1394 packet either corresponds tothe BMP protocol or to the IP protocol. The following protocols aredefined: BMP (0101₁₆); IP (0800₁₆). In this manner, the protocol of thepacket, according to the configuration of the system as shown in FIG. 5,can be identified to the IEEE 1394 indicating the type of data containedin the data field. The protocol_type field may be modified based on theconfiguration of the system to indicate the type of packet encapsulatedin the field. Thus, the IEEE 1394 memory read write function is modifiedso that, instead of parsing the fields to determine where to write to orread from, the function examines the protocol_type to determine wherethe packet is from and thereafter how to process the packet.

[0093] Other fields in the Common Packet Header include: destination_IDwhich specifies the IEEE 1394 node ID of the receiving node (asdiscussed above with reference to FIG. 7A); t1 which is the transactionlabel (unused and set to zero); rt which is the retry code (the networkdoes not use the IEEE 1394 capability to resend data if the data thatwas previously send was not received properly; therefore, the retry codeis set to zero); tcode which is the transaction code specifying thepacket format and type of transaction to be performed (the IEEE 1394receivers use the tcode to determine the 1394 header format); pri whichis the priority (this field is unused and set to zero); source ID whichspecifies the IEEE 1394 node ID of the sending node (with the format ofFIG. 7A); protocol type which specifies the protocol of the packetencapsulated in the data field (two protocols are defined, one for theBMP and one for IP); pn_version which is the network version number;company_ID which is discussed subsequently; data length which is thetotal length of the data field in the number of bytes; extended_tcode isthe extended transaction code which is set to zero; header CRC which isthe computed cyclic redundancy check for the CPH portion of the packet;data field which is the data to be transferred in the packet; anddata_CRC which is the computed cyclic redundancy check, using the samealgorithm used to compute the header_CRC.

[0094] Further, if the IP packet is not a multiple of 4, then the datafield is padded by one or more zero bytes to align the data field end ona quadlet boundary. The IP packet is then followed by the cyclicredundancy check (CRC) which checks the integrity of the data field.

[0095] The company_ID indicates the specific company that manufacturedthe network and is used as a packet identifier or a data streamidentifier (i.e. identifying the origin of the packet or the datastream). This is added in the common packet header in order to addrobustness to the system. The company_ID is used (1) in terms ofassigning addresses and (2) in terms of determining whether to process apacket. First, after a node is inserted or removed from the network, theIP addresses are assigned, during the Manager Identify phase 168, thesame IP addresses prior to insertion or removal of the node. During theManager Identify phase 168, the node sends a Get-Priority-Response inresponse to a Get-Priority-Request. Encapsulated in theGet-Priority-Response is the common packet header (CPH) as shown in FIG.7C. The common packet header contains the company_ID which is sent bythe module 204 sending the Get-Priority-Response to the Manager of theNetwork 190. The module 204 accesses ROM 210 to retrieve the company_ID202 to formulate the common packet header. The Manager of the Network190, when assigning IP addresses during the Manger Identify phase 168,determines whether a node is network compatible, based on the company_IDin the Get-Priority-Response. The Manager of the Network 190 uses thecomparator 194 in the processor 192 to determine whether the company_IDfield in the packet header is the same as the value stored in the ROM200 of the Network Manager 190. If the values are not the same, theManager of the Network 190 does not assign an IP address to the node ofthe module which sent the Get-Priority-Response which did not containthe company_ID in the common packet header. In this manner, non-networkmodules do not interact with the higher layers of the computerarchitecture.

[0096] Second, it is important that non-network packets are discarded bythe network with as little effect on the network as possible. In orderto do this, each packet includes a specific manufacture identifier(company_ID) in the common packet header so that if any packet does notcontain a valid company identifier field, it will be discarded by thereceiver. Each module which is connected to the network via nodes 214determines what the company_ID is. The sender module contains thecompany_ID 202 in its ROM 200. FIG. 8 shows that the sender module isthe network manager 190. The sender module may be any network compatiblemodule, including the network manager 190. The sender module retrievesthe company_ID and formats the packet header with the company_ID inconformance with FIG. 7C. The sender module then sends the packet ontothe bus. A module 204 receives the packet and determines whether toprocess the packet based on the field allocated to the company_ID. Themodule performs this receiving of the packet at the link layer. Thecompany_ID 202 is hardwired into the module via a Read Only Memory (ROM)210. Alternatively, the company_ID is sent to all modules during anyreset to the bus so that the company_ID can reside in volatile memory.

[0097] Referring to FIG. 9, the module which receives the packet firstdetermines the company_ID for compatible modules 216. When the modulereceives a packet from the bus 218, the module uses its processor 206searches the packet header 220. The module then compares the packet withthe company_ID using the comparator 208. If the header contains thecompany_ID in the correct portion of the header 222, the moduleprocesses the packet 224. Otherwise, the packet is not processed. Thus,if a non-network compatible device is connected to the system, moduleswhich are not designed to process the packet may refuse the packet atthe link layer and thereby not interfere with the module's processing.

[0098] From the foregoing detailed description, it will be appreciatedthat numerous changes and modifications can be made to the hardware andsoftware aspects of the invention without departure from the true spiritand scope of the invention. For example, the present invention is notdependent on any specific type of computer architecture or type ofprotocol. This true spirit and scope of the invention is defined by theappended claims, to be interpreted in light of the foregoingspecification.

We claim:
 1. In a data processing system having a network bus, at leastone component connected to a node on the network bus and a networkmanager connected to the network bus having a memory containing alook-up table, the component containing a non-changeable address whichdoes not change upon reconfiguration of the network and the componentbeing assigned a changeable address, a method for reconfiguring thenetwork without disturbing the on-going traffic comprising the steps of:A. obtaining the non-changeable address and changeable address for theat least one component; B. placing the non-changeable address andchangeable address for the at least one component in the look-up table;C. reconfiguring the network; D. determining the non-changeable addressfor the at least one component; E. examining in the look-up table thechangeable address for the at least one component which corresponds tothe non-changeable address; and F. assigning the at least one componentwith the address which corresponds to the changeable address in thelook-up table.
 2. The method of claim 1 wherein the step ofreconfiguring the network includes inserting a component onto a node ofthe network bus.
 3. The method of claim 1 wherein the step ofreconfiguring the network includes removing a component from a node ofthe network bus.
 4. The method of claim 1 wherein the step ofdetermining the non-changeable address for the at least one componentincludes reading a network identification address in a non-volatilememory device.
 5. The method of claim 4 wherein the non-volatile memorydevice is a Read Only Memory device which is programmed duringmanufacture.
 6. The method of claim 1 further comprising the step ofdynamically generating the at least one component with a secondchangeable address.
 7. The method of claim 6 wherein the look-up tablefurther contains a second changeable address for the at least onecomponent prior to reconfiguring the network and further comprising thestep of updating the look-up table with the second changeable addressafter the step of dynamically generating the at least one component witha second changeable address.
 8. The method of claim 6 wherein the firstchangeable address is formatted under the Internet Protocol and thesecond changeable address is formatted under the IEEE 1394 protocol. 9.In a data processing system having a computer architecture with avertical set of layers, the data processing system having a network bus,at least one component connected to a node on the network bus and anetwork manager connected to the network bus having a memory containinga look-up table, the component containing a non-changeable address whichdoes not change upon reconfiguration of the network, and the componentbeing assigned two changeable address which can change uponreconfiguring the network, the first changeable address being assignablefor a higher layer and the second changeable address being dynamicallygenerated for a lower layer, a method for reconfiguring-the networkwithout disturbing the on-going traffic on the higher layer and onlayers higher than the higher layer comprising the steps of: A.obtaining the non-changeable address and first changeable address forthe at least one component; B. placing the non-changeable address andfirst changeable address for the at least one component in the look-uptable; C. reconfiguring the network; D. determining the non-changeableaddress for the at least one component; E. examining in the look-uptable the first changeable address for the at least one component priorto reconfiguring the network that corresponds to the non-changeableaddress; and F. assigning the at least one component with the addresswhich corresponds to the first changeable address for the at least onecomponent prior to reconfiguring the network in the look-up table. 10.The method of claim 9 wherein the step of reconfiguring the networkincludes inserting a component onto a node on the network bus.
 11. Themethod of claim 9 wherein the step of reconfiguring the network includesremoving a component from a node on the network bus.
 12. The method ofclaim 9 wherein the look-up table further contains the second changeableaddress for the at least one component prior to reconfiguring thenetwork and further comprising the steps of dynamically generating theat least one component with a new second changeable address and updatingthe look-up table with the new second changeable address.
 13. The methodof claim 9 wherein the step of determining the non-changeable addressfor the at least one component includes reading a network identificationaddress in a non-volatile memory device.
 14. The method of claim 9wherein the first changeable address is formatted under the InternetProtocol and the second changeable address is formatted under the IEEE1394 protocol.
 15. In a data processing system having a network bus, atleast one component connected to a node on the network bus and a networkmanager connected to the network bus having a memory containing alook-up table, the component containing a non-changeable address whichcannot change upon reconfiguring the network, and the component beingassigned two changeable addresses which can change upon reconfiguringthe network and which are assignable, a method for reconfiguring thenetwork without disturbing the on-going traffic comprising the steps of:A. obtaining the non-changeable address and two changeable addresses forthe at least one component; B. placing the non-changeable address andtwo changeable addresses for the at least one component in the look-uptable; C. reconfiguring the network; D. determining the non-changeableaddress for the at least one node; E. examining in the look-up table thefirst changeable address that corresponds to the non-changeable address;F. examining in the look-up table the second changeable address thatcorresponds to the non-changeable address; G. assigning the at least onecomponent with the address which corresponds to the first changeableaddress for the at least one component prior to reconfiguring thenetwork in the look-up table; and H. assigning the at least onecomponent with the address which corresponds to the second changeableaddress for the at least one component prior to reconfiguring thenetwork in the look-up table.
 16. A data processing system forinterconnecting components along a network, the data processing systemcomprising: a bus line having at least two nodes; a module connected tothe first node, the module including a non-volatile memory, thenon-volatile memory containing a network identifier address, the modulealso being assigned a changeable address; a network manager connected tothe second node, the network manager having a memory device and aprocessor, the memory device having a look-up table, the look-up tablecontaining the network identifier address for the module and thechangeable address of the module; and the processor having a comparator,the comparator comparing the network identifier address in the look-uptable with the network identifier address in the module, the processorassigning the module the changeable address in the look-up table if thenetwork identifier address in the look-up table equals the networkidentifier address in the module.
 17. A data processing system forinterconnecting components along a network, the data processing systemhaving a computer architecture with a vertical set of layers, the dataprocessing system comprising: a module being assigned an address for alayer in the computer architecture, the module including a non-volatilememory, the non-volatile memory containing a network identifier address,the module also being assigned a changeable address for the layer whichis assignable; a network manager having a memory device and a processor;the memory device having a look-up table, the look-up table containingthe module's network identifier address and the module's changeableaddress for the layer; and the processor having a comparator, thecomparator comparing the network identifier address in the look-up tablewith the network identifier address in the module, the processorassigning the module the changeable address in the look-up table for thelayer of the module if the network identifier address in the look-uptable equals the network identifier address in the module.
 18. A dataprocessing system as claimed in claim 17 wherein the layer that themodule is connected to is the network layer.
 19. A data processingsystem as claimed in claim 18 wherein the network layer is formattedunder the Internet Protocol.
 20. A data processing system forinterconnecting components along a network, the data processing systemhaving a computer architecture with a vertical set of layers, the dataprocessing system comprising: a data network including an upper layerand a lower layer in the computer architecture; a module connected tothe data network, the module including a non-volatile memory, thenon-volatile memory containing a network identifier address, the modulealso being assigned a changeable address for the upper layer; a networkmanager connected to the data network, the network manager having amemory device and a processor; the memory device having a look-up table,the look-up table containing the module's network identifier address andthe module's changeable address for the layer; and the processor havinga comparator, the comparator comparing the network identifier address inthe look-up table with the network identifier address in the module, theprocessor assigning the module the changeable address in the look-uptable for the upper layer if the network identifier address in thelook-up table equals the network identifier address in the module.
 21. Adata processing system as claimed in claim 20 wherein the module has asecond changeable address for the lower layer which is dynamicallygenerated.
 22. A data processing system as claimed in claim 21 whereinthe lower layer is formatted under the IEEE 1394 protocol.
 23. A dataprocessing system as claimed in claim 20 wherein the upper layer isformatted under the Internet Protocol.
 24. In a data processing systemhaving a network bus and having a protocol for a data stream wherein thedata stream has a header with fields, one field being the data streamidentifier field, a component connected to the network bus, thecomponent having a memory device containing a data stream identifier,the component also having a processor, the processor having acomparator, a method for determining whether to process an incoming datastream comprising the steps of: A. obtaining the data stream identifierfrom the memory device of the component; B. receiving the incoming datastream by the component; C. parsing through the header of the datastream to obtain the data in the data stream identifier field; D.comparing the data which was parsed with the data stream identifier fromthe memory device of the component; and E. processing the incoming datastream if the data which was parsed equals the data stream identifierfrom the memory device of the component.
 25. The method of claim 24wherein the incoming data stream is in the form of a packet of data. 26.The method of claim 24 wherein the data stream identifier from thememory device of the component is a company identification number. 27.In a data processing system having a network bus and having a protocolfor a data stream wherein the data stream has a header with fields, onefield being the data stream identifier field, a first component and asecond component both connected to the network bus, the first componenthaving a first memory device containing a first data stream identifier,the first component also having a first processor, the second componenthaving a second memory device containing a second data streamidentifier, the second component also having a second processor, thesecond processor having a comparator, a method for determining whetherto process an incoming data stream comprising the steps of: A. obtainingthe first data stream identifier from the first memory device; B.forming a data stream by inserting the first data stream identifier inthe data stream identifier field; C. sending the data stream onto thebus; D. obtaining the second data stream identifier from the secondmemory device of the second component; E. receiving the data stream bythe second component; F. parsing through the header of the data streamto obtain the data in the data stream identifier field; G. comparing thedata which was parsed with the second data stream identifier; and H.processing the incoming data stream if the data which was parsed equalsthe second data stream identifier.
 28. The method of claim 27 whereinthe incoming data stream is in the form of a packet of data.
 29. Themethod of claim 28 wherein the first data stream identifier is a firstcompany identification number and the second data stream identifier is asecond company identification number.
 30. A data processing system forinterconnecting components along a network and for processing packets ofdata, the packets of data having a protocol wherein the packets have aheader with fields, one field being the packet identifier fieldcontaining a packet identifier, the packet identifier identifying theorigin of the packet, the data processing system comprising: a bus linehaving at least two nodes; a first module connected to the first node,the first module including a first memory, the first memory containing afirst packet identifier, the module also including a first processor;the first processor forming the data stream including the header, thefirst processor connected to the first memory, the first processoraccessing the first memory to obtain the first packet identifier, thefirst processor placing the first packet identifier in the packetidentifier field; a second module connected to the second node, thesecond module including a second memory, the second memory containing asecond packet identifier, the module also including a second processor;the second processor having a comparator, the comparator comparing thesecond packet identifier in the second memory with the data in thepacket identifier field, the second processor processing the packet ifthe second packet identifier in the second memory equals the data in thepacket identifier field.
 31. A data processing system as claimed inclaim 30 wherein the first packet identifier is a first companyidentification number and the second packet identifier is a secondcompany identification number.
 32. In a data processing system having aprotocol for a packet wherein the packet has a header with fields, onefield being the company identifier field, the data processing systemalso having a network bus, at least one component connected to a node onthe network bus and a network manager connected to the network bushaving a processor, the processor having a comparator, the networkmanager also having a memory containing a first company identifier, thecomponent having a memory containing a second company identifier, amethod for assigning addresses to a company compatible componentcomprising the steps of: A. obtaining the second company identifier fromthe memory device of the component; B. forming a packet of data in thecomponent by inserting the second company identifier in the companyidentifier field; C. sending the packet of data onto the bus; D.obtaining the first company identifier from the memory device of thenetwork manager; E. receiving the packet of data by the network manager;F. parsing through the header of the packet of data to obtain the datain the company identifier field; G. comparing, in the comparator of thenetwork manager, the data which was parsed with the first companyidentifier obtained from the memory device of the network manager; andH. assigning an address to the component if the data which was parsedequals the first company identifier.
 33. The method of claim 32 whereinthe data processing system is composed of a vertical set of layers, oneof which is a network layer, and wherein the address assigned to thecomponent if the data which was parsed equals the first companyidentifier is at the network layer.
 34. In a data processing systemhaving a sender module for sending information and a receiver module forreceiving information, the data processing system also having a computerarchitecture with a vertical set of layers, the computer architecturehaving a physical layer, link layer and network layer, the physical andlink layers configured under a standard which dictates that memoryarchitecture information be included in a packet of information sentfrom the sender module to the receiver module, the physical and linklayers having a memory read write function, the network layer configuredunder a standard which dictates channel based I/O and which does notinclude memory architecture information in the packet of data sent fromthe sender module to the receiver module, a method for sending a packetof data on a physical and link layer configured for packets whichinclude memory architecture information in the packet comprising thesteps of: receiving from the sender module the packet of information atthe link layer from the network layer; placing header information intothe packet which does not include memory architecture information aboutthe receiver module and which conforms to sending the information viachannel based I/O; and transporting, via the physical layer, the packetto the receiver module including executing the memory read writefunction without examining the header of the packet of information formemory architecture information.
 35. The method of claim 34 wherein thenetwork layer is formatted under the Internet Protocol and the physicaland link layers are formatted under the IEEE 1394 protocol.
 36. Themethod of claim 35 further comprising the step of modifying the memoryread write function of physical and link layers to execute channel basedI/O.
 37. The method of claim 34 wherein the sender module has a memorycontaining a first company identifier and further comprising the step ofinserting in the header of the packet the first company identifier. 38.The method of claim 37 wherein the receiver module has a memorycontaining a second company identifier and further comprising the stepsof parsing through the packet of information for the company identifierand comparing the parsed information with the second company identifierin the memory of the receiver module.
 39. The method of claim 38 furthercomprising the step of processing the packet if the parsed informationequals the second company identifier in the memory of the receivermodule.
 40. In a data processing system having a sender module forsending information and a receiver module for receiving information, thedata processing system also having a computer architecture with avertical set of layers, the computer architecture having a physicallayer and link layer formatted under the IEEE 1394 standard and anetwork layer formatted under the Internet Protocol, the IEEE 1394standard dictating that memory architecture information be included in apacket of information sent from the sender module to the receivermodule, the Internet Protocol standard dictating that packets ofinformation do not include memory architecture information sent from thesender module to the receiver module, a method for sending a packet ofdata on an IEEE 1394 physical and link layer and on an Internet Protocolnetwork layer comprising the steps of: receiving the packet oninformation at the network layer from the sender module; formatting thepacket with information conforming to the Internet Protocol includingplacing header information into the packet which does not include memoryarchitecture information about the receiver module; sending the packetof information from the network layer to the physical and link layer;transporting via the IEEE 1394 physical and link layer the packet to thereceiver module using a memory read write protocol which does notrequire memory architecture of the receiver module; and processing thepacket of information by the receiver module.
 41. A data communicationssystem comprising: a network having a first node and a second node; acall terminating device connected to the first node of the network, thecall terminating device comprising a framer, a time division multiplexline, and at least one modem, the call terminating device connected tothe first node, the module including a non-volatile memory, thenon-volatile memory containing a network identifier address, the modulealso being assigned a changeable address; a router device connected tothe second node of the network, the router device having a memory deviceand a processor, the memory device having a look-up table, the look-uptable containing the network identifier address for the module and thechangeable address of the module; and the processor having a comparator,the comparator comparing the network identifier address in the look-uptable with the network identifier address in the call terminatingdevice, the processor assigning the call terminating device thechangeable address in the look-up table if the network identifieraddress in the look-up table equals the network identifier address inthe call terminating device.
 42. The data communications system of claim41 wherein the changeable address is formatted under the InternetProtocol.
 43. The data communications system of claim 41 wherein thenetwork is an IEEE 1394 network.